Count clock/HDLBits

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module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    reg clkm,clkh;
    always@(posedge clk)
        begin
            if(reset)
                    ss=0;
            else if(ena==1)
                begin
                    if(ss[3:0]==9)
                        if(ss[7:4]==5)
                            ss=0;
                    	else begin
                            ss[7:4]=ss[7:4]+1;
                            ss[3:0]=0;
                        end
                    else 
                            ss[3:0]=ss[3:0]+1;
                end
        end
    always@(posedge clk)
        begin
            if(reset)
                mm=0;
           else if(ena)
                    begin
                        if(ss[7:4]==5&&ss[3:0]==9)
                        if(mm[3:0]==9)
                            if(mm[7:4]==5)
                                    mm=0;
                        	else begin
                                mm[7:4]=mm[7:4]+1;
                                mm[3:0]=0;
                            end
                        else mm[3:0]=mm[3:0]+1;
                    end
        end
    always@(posedge clk)
        begin
            if(reset)
                begin
                    hh[3:0]=2;
                    hh[7:4]=1;
                end
           else if(ena)
                begin
                 if(mm[7:4]==5&&mm[3:0]==9&&ss[7:4]==5&&ss[3:0]==9)
                     if(hh[7:4]==0&&hh[3:0]==9)
                        begin
                        hh[3:0]=0;
                    	hh[7:4]=1;
                   		end
                    else if(hh[7:4]==1&&hh[3:0]==1)
                        begin
                             pm=~pm;
                             hh[3:0]=2;
                           end
                    else if(hh[7:4]==1&&hh[3:0]==2)
                        begin
                            hh[7:4]=0;
                            hh[3:0]=1;
                        end
                    else hh[3:0]=hh[3:0]+1;
                end
        end
endmodule

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module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    reg clkm,clkh;
    always@(posedge clk)
        begin
            if(reset)
                    ss=0;
            else if(ena==1)
                begin
                    if(ss[3:0]==9)
                        if(ss[7:4]==5)
                            ss=0;
                    	else begin
                            ss[7:4]=ss[7:4]+1;
                            ss[3:0]=0;
                        end
                    else 
                            ss[3:0]=ss[3:0]+1;
                end
        end
    always@(posedge clk)
        begin
            if(reset)
                mm=0;
           else if(ena)
                    begin
                        if(ss[7:4]==5&&ss[3:0]==9)
                        if(mm[3:0]==9)
                            if(mm[7:4]==5)
                                    mm=0;
                        	else begin
                                mm[7:4]=mm[7:4]+1;
                                mm[3:0]=0;
                            end
                        else mm[3:0]=mm[3:0]+1;
                    end
        end
    always@(posedge clk)
        begin
            if(reset)
                begin
                    hh[3:0]=2;
                    hh[7:4]=1;
                end
           else if(ena)
                begin
                 if(mm[7:4]==5&&mm[3:0]==9&&ss[7:4]==5&&ss[3:0]==9)
                     if(hh[7:4]==0&&hh[3:0]==9)
                        begin
                        hh[3:0]=0;
                    	hh[7:4]=1;
                   		end
                    else if(hh[7:4]==1&&hh[3:0]==1)
                        begin
                             pm=~pm;
                             hh[3:0]=2;
                           end
                    else if(hh[7:4]==1&&hh[3:0]==2)
                        begin
                            hh[7:4]=0;
                            hh[3:0]=1;
                        end
                    else hh[3:0]=hh[3:0]+1;
                end
        end
endmodule