EDA数字钟设计（verilog）——计时模块

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module jishi(clk_1Hz,second,minute,hour,hour_swh,min_swh,swh,baochi_swh);

input clk_1Hz;
input hour_swh,min_swh,baochi_swh;
input [1:0]swh;
output reg[5:0]second,minute,hour;
reg [11:0]hs; //3600秒小时加1

always@(posedge clk_1Hz)
	begin
		if((swh[1:0] == 'b00)&&(!baochi_swh))  //清零
			begin
				second <= 0;
				minute <= 0;
				hour <= 0;
		    end
		else if(baochi_swh)  //使能
		    begin
				second <= second;
				minute <= minute;
				hour <= hour;
		    end
		else if((swh[1:0] == 'b11)&&(!baochi_swh))   //正常计数
			begin
				if(second < 'd59)
					begin
						second <= second + 'd1;
						hs <= hs + 'd1;
					end
				else
					begin
						second <= 'd0;
						hs <= hs + 'd1;
						if(minute < 'd59)
							minute <= minute + 'd1;
						else
							minute <= 'd0;
						if(hs < 'd3599 && hour < 'd23)
							hour <= hour + 'd1;
						else if((hs == 'd3599)&&(hour == 'd23))
							begin
								hour <= 'd0;
								hs <= 'd0;
							end
					end
			end
		else if((swh[1:0] == 'b10)&&(!baochi_swh))  //显示学号
			begin
				hour <= 'd00;
				minute <= 'd07;
				second <= 'd36;
			end
		else if((swh[1:0] == 'b01)&&(!baochi_swh)) 
			begin
				if((hour_swh)&&(swh[1:0] == 'b01))
					begin
						if(hour == 'd23)
							hour <= 'd0;
						else
							hour <= hour + 'd1;
					end
				if((min_swh)&&(swh[1:0] == 'b01))
					begin
						if(minute == 'd59)
							minute <= 'd0;
						else
							minute <= minute + 'd1;
					end
			end
	end  
			
endmodule