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module Tff_2
(
  input      clk   ,
  input      rst_n ,
  input      data  ,

  output reg q1
);

reg data_buf;

always @ (posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    data_buf <= 1'b0;
  end
  else if (data == 1) begin
    data_buf <= ~data_buf;
  end
  else begin
    data_buf <= data_buf;
  end
end


always @ (posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    q1 <= 1'b0;
  end
  else if (data_buf == 1) begin
    q1 <= ~q1;
  end
  else begin
    q1 <= q1;
  end
end

endmodule

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`timescale 1ps/1ps

module tb_Tff_2;

  reg  clk   ;
  reg  rst_n ;
  reg  data  ;
  
  wire q1    ;
  
/*-----------------------------------------------
 -- data | data_buf | next_data_buf --
 --   0  |     0    |       0       --
 --   0  |     1    |       1       --
 --   1  |     0    |       1       --
 --   1  |     1    |       0       --
-----------------------------------------------*/

initial begin
  clk   = 1;
  rst_n = 1;
  data  = 0;
  #2500 rst_n = 0;  
  #5000 rst_n = 1;  
  repeat(5)begin
    case_4(data,1);
  end

  repeat(5)begin
    case_4(data,0);
  end

  repeat(5)begin
    case_4(data,1);
  end
  
  repeat(100)begin
    case_random(data); 
  end
end

/*-----------------------------------------------
 --    --
-----------------------------------------------*/
task case_4;
  output  a;
  input   b;

  case(b)
    0: #5000 a = 0;
    1: #5000 a = 1;
  endcase
endtask

task case_random;
  output  a;
  #5000 a = {$random}%2;
endtask

/*-----------------------------------------------
 --  clock period is 5ns  --
-----------------------------------------------*/
always begin
  #2500 clk = ~clk;
end

/*-----------------------------------------------
 --  display  --
-----------------------------------------------*/
always @ (posedge clk ) begin               
    $display("data = %d ; data_buf = %d ; q1 = %d",data,Tff_2.data_buf,q1);
end

Tff_2 tb_Tff_2(
                 .clk     (clk  ),
                 .rst_n   (rst_n),
                 .data    (data ),
                 .q1      (q1   )
              );

initial #350000 $finish;
initial begin
  $fsdbDumpfile("Tff_2.fsdb");
  $fsdbDumpvars            ;
  $fsdbDumpMDA             ;
end
endmodule