vhdl 状态机

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• 4-State Mealy State Machine 

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The outputs of a Mealy state machine depend on both the inputs and the current state. When the inputs change, the outputs are updated without waiting for a clock edge.

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• 4-State Moore State Machine 

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The outputs of a Moore state machine depend only on the present state. The outputs are written only when the state changes (on the clock edge).

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• Safe State Machine 

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This example uses the syn_encoding synthesis attribute value safe to specify that the software should insert extra logic to detect an illegal state and force the state machine's transition to the reset state.

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• User-Encoded State Machine 

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This example uses the syn_encoding synthesis attribute to apply specific binary encodings to the elements of an enumerated type.

 

复制代码 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity safe_state is 5 6 port( 7 clk : in std_logic; 8 data_in : in std_logic; 9 reset : in std_logic; 10 data_out : out std_logic_vector(1 downto 0) 11 ); 12 13 end entity; 14 15 architecture rtl of safe_state is 16 17 -- Build an enumerated type for the state machine 18 type state_type is (s0, s1, s2); 19 20 -- Register to hold the current state 21 signal state : state_type; 22 23 -- Attribute "safe" implements a safe state machine. 24 -- This is a state machine that can recover from an 25 -- illegal state (by returning to the reset state). 26 attribute syn_encoding : string; 27 attribute syn_encoding of state_type : type is "safe"; 28 29 begin 30 31 -- Logic to advance to the next state 32 process (clk, reset) 33 begin 34 if reset = '1' then 35 state <= s0; 36 elsif (rising_edge(clk)) then 37 case state is 38 when s0 => 39 if data_in = '1' then 40 state <= s1; 41 else 42 state <= s0; 43 end if; 44 when s1 => 45 if data_in = '1' then 46 state <= s2; 47 else 48 state <= s1; 49 end if; 50 when s2 => 51 if data_in = '1' then 52 state <= s0; 53 else 54 state <= s2; 55 end if; 56 end case; 57 end if; 58 end process; 59 60 -- Logic to determine output 61 process (state) 62 begin 63 case state is 64 when s0 => 65 data_out <= "00"; 66 when s1 => 67 data_out <= "01"; 68 when s2 => 69 data_out <= "10"; 70 end case; 71 end process; 72 73 end rtl; 74 75 -- A Mealy machine has outputs that depend on both the state and 76 -- the inputs. When the inputs change, the outputs are updated 77 -- immediately, without waiting for a clock edge. The outputs 78 -- can be written more than once per state or per clock cycle. 79 80 library ieee; 81 use ieee.std_logic_1164.all; 82 83 entity mealy_4s is 84 85 port 86 ( 87 clk : in std_logic; 88 data_in : in std_logic; 89 reset : in std_logic; 90 data_out : out std_logic_vector(1 downto 0) 91 ); 92 93 end entity; 94 95 architecture rtl of mealy_4s is 96 97 -- Build an enumerated type for the state machine 98 type state_type is (s0, s1, s2, s3); 99 100 -- Register to hold the current state 101 signal state : state_type; 102 103 begin 104 process (clk, reset) 105 begin 106 if reset = '1' then 107 state <= s0; 108 elsif (rising_edge(clk)) then 109 -- Determine the next state synchronously, based on 110 -- the current state and the input 111 case state is 112 when s0 => 113 if data_in = '1' then 114 state <= s1; 115 else 116 state <= s0; 117 end if; 118 when s1 => 119 if data_in = '1' then 120 state <= s2; 121 else 122 state <= s1; 123 end if; 124 when s2 => 125 if data_in = '1' then 126 state <= s3; 127 else 128 state <= s2; 129 end if; 130 when s3 => 131 if data_in = '1' then 132 state <= s3; 133 else 134 state <= s1; 135 end if; 136 end case; 137 138 end if; 139 end process; 140 141 -- Determine the output based only on the current state 142 -- and the input (do not wait for a clock edge). 143 process (state, data_in) 144 begin 145 case state is 146 when s0 => 147 if data_in = '1' then 148 data_out <= "00"; 149 else 150 data_out <= "01"; 151 end if; 152 when s1 => 153 if data_in = '1' then 154 data_out <= "01"; 155 else 156 data_out <= "11"; 157 end if; 158 when s2 => 159 if data_in = '1' then 160 data_out <= "10"; 161 else 162 data_out <= "10"; 163 end if; 164 when s3 => 165 if data_in = '1' then 166 data_out <= "11"; 167 else 168 data_out <= "10"; 169 end if; 170 end case; 171 end process; 172 173 end rtl; 174 175 176 -- A Moore machine's outputs are dependent only on the current state. 177 -- The output is written only when the state changes. (State 178 -- transitions are synchronous.) 179 180 library ieee; 181 use ieee.std_logic_1164.all; 182 183 entity moore_4s is 184 185 port( 186 clk : in std_logic; 187 data_in : in std_logic; 188 reset : in std_logic; 189 data_out : out std_logic_vector(1 downto 0) 190 ); 191 192 end entity; 193 194 architecture rtl of moore_4s is 195 196 -- Build an enumerated type for the state machine 197 type state_type is (s0, s1, s2, s3); 198 199 -- Register to hold the current state 200 signal state : state_type; 201 202 begin 203 -- Logic to advance to the next state 204 process (clk, reset) 205 begin 206 if reset = '1' then 207 state <= s0; 208 elsif (rising_edge(clk)) then 209 case state is 210 when s0 => 211 if data_in = '1' then 212 state <= s1; 213 else 214 state <= s0; 215 end if; 216 when s1 => 217 if data_in = '1' then 218 state <= s2; 219 else 220 state <= s1; 221 end if; 222 when s2 => 223 if data_in = '1' then 224 state <= s3; 225 else 226 state <= s2; 227 end if; 228 when s3 => 229 if data_in = '1' then 230 state <= s0; 231 else 232 state <= s3; 233 end if; 234 end case; 235 end if; 236 end process; 237 238 -- Output depends solely on the current state 239 process (state) 240 begin 241 242 case state is 243 when s0 => 244 data_out <= "00"; 245 when s1 => 246 data_out <= "01"; 247 when s2 => 248 data_out <= "10"; 249 when s3 => 250 data_out <= "11"; 251 end case; 252 end process; 253 254 end rtl; 255 256 257 -- User-Encoded State Machine 258 259 library ieee; 260 use ieee.std_logic_1164.all; 261 262 entity user_encod is 263 264 port 265 ( 266 updown : in std_logic; 267 clock : in std_logic; 268 lsb : out std_logic; 269 msb : out std_logic 270 ); 271 272 end entity; 273 274 architecture rtl of user_encod is 275 276 -- Build an enumerated type for the state machine 277 type count_state is (zero, one, two, three); 278 279 -- Registers to hold the current state and the next state 280 signal present_state, next_state : count_state; 281 282 -- Attribute to declare a specific encoding for the states 283 attribute syn_encoding : string; 284 attribute syn_encoding of count_state : type is "11 01 10 00"; 285 286 begin 287 288 -- Determine what the next state will be, and set the output bits 289 process (present_state, updown) 290 begin 291 case present_state is 292 when zero => 293 if (updown = '0') then 294 next_state <= one; 295 lsb <= '0'; 296 msb <= '0'; 297 else 298 next_state <= three; 299 lsb <= '1'; 300 msb <= '1'; 301 end if; 302 when one => 303 if (updown = '0') then 304 next_state <= two; 305 lsb <= '1'; 306 msb <= '0'; 307 else 308 next_state <= zero; 309 lsb <= '0'; 310 msb <= '0'; 311 end if; 312 when two => 313 if (updown = '0') then 314 next_state <= three; 315 lsb <= '0'; 316 msb <= '1'; 317 else 318 next_state <= one; 319 lsb <= '1'; 320 msb <= '0'; 321 end if; 322 when three => 323 if (updown = '0') then 324 next_state <= zero; 325 lsb <= '1'; 326 msb <= '1'; 327 else 328 next_state <= two; 329 lsb <= '0'; 330 msb <= '1'; 331 end if; 332 end case; 333 end process; 334 335 -- Move to the next state 336 process 337 begin 338 wait until rising_edge(clock); 339 present_state <= next_state; 340 end process; 341 342 end rtl;

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  1 library ieee;
use ieee.std_logic_1164.all;

entity safe_state is

  port(
    clk      : in std_logic;
    data_in  : in std_logic;
    reset    : in std_logic;
    data_out : out  std_logic_vector(1 downto 0)
  );

end entity;

architecture rtl of safe_state is

  -- Build an enumerated type for the state machine
  type state_type is (s0, s1, s2);

  -- Register to hold the current state
  signal state : state_type;

  -- Attribute "safe" implements a safe state machine.
  -- This is a state machine that can recover from an
  -- illegal state (by returning to the reset state).
  attribute syn_encoding               : string;
  attribute syn_encoding of state_type : type is "safe";

begin

  -- Logic to advance to the next state
  process (clk, reset)
  begin
    if reset = '1' then
      state <= s0;
    elsif (rising_edge(clk)) then
      case state is
        when s0 =>
          if data_in = '1' then
            state <= s1;
          else
            state <= s0;
          end if;
        when s1 =>
          if data_in = '1' then
            state <= s2;
          else
            state <= s1;
          end if;
        when s2 =>
          if data_in = '1' then
            state <= s0;
          else
            state <= s2;
          end if;
      end case;
    end if;
  end process;

  -- Logic to determine output
  process (state)
  begin
    case state is
      when s0 =>
        data_out <= "00";
      when s1 =>
        data_out <= "01";
      when s2 =>
        data_out <= "10";
    end case;
  end process;

end rtl;

-- A Mealy machine has outputs that depend on both the state and
-- the inputs.  When the inputs change, the outputs are updated
-- immediately, without waiting for a clock edge.  The outputs
-- can be written more than once per state or per clock cycle.

library ieee;
use ieee.std_logic_1164.all;

entity mealy_4s is

  port
  (
    clk      : in std_logic;
    data_in  : in std_logic;
    reset    : in std_logic;
    data_out : out  std_logic_vector(1 downto 0)
  );

end entity;

architecture rtl of mealy_4s is

  -- Build an enumerated type for the state machine
  type state_type is (s0, s1, s2, s3);

  -- Register to hold the current state
  signal state : state_type;

begin
  process (clk, reset)
  begin
    if reset = '1' then
      state <= s0;
    elsif (rising_edge(clk)) then
      -- Determine the next state synchronously, based on
      -- the current state and the input
      case state is
        when s0 =>
          if data_in = '1' then
            state <= s1;
          else
            state <= s0;
          end if;
        when s1 =>
          if data_in = '1' then
            state <= s2;
          else
            state <= s1;
          end if;
        when s2 =>
          if data_in = '1' then
            state <= s3;
          else
            state <= s2;
          end if;
        when s3 =>
          if data_in = '1' then
            state <= s3;
          else
            state <= s1;
          end if;
      end case;

    end if;
  end process;

  -- Determine the output based only on the current state
  -- and the input (do not wait for a clock edge).
  process (state, data_in)
  begin
    case state is
      when s0 =>
        if data_in = '1' then
          data_out <= "00";
        else
          data_out <= "01";
        end if;
      when s1 =>
        if data_in = '1' then
          data_out <= "01";
        else
          data_out <= "11";
        end if;
      when s2 =>
        if data_in = '1' then
          data_out <= "10";
        else
          data_out <= "10";
        end if;
      when s3 =>
        if data_in = '1' then
          data_out <= "11";
        else
          data_out <= "10";
        end if;
    end case;
  end process;

end rtl;


-- A Moore machine's outputs are dependent only on the current state.
-- The output is written only when the state changes.  (State
-- transitions are synchronous.)

library ieee;
use ieee.std_logic_1164.all;

entity moore_4s is

  port(
    clk      : in std_logic;
    data_in  : in std_logic;
    reset    : in std_logic;
    data_out : out  std_logic_vector(1 downto 0)
  );

end entity;

architecture rtl of moore_4s is

  -- Build an enumerated type for the state machine
  type state_type is (s0, s1, s2, s3);

  -- Register to hold the current state
  signal state : state_type;

begin
  -- Logic to advance to the next state
  process (clk, reset)
  begin
    if reset = '1' then
      state <= s0;
    elsif (rising_edge(clk)) then
      case state is
        when s0 =>
          if data_in = '1' then
            state <= s1;
          else
            state <= s0;
          end if;
        when s1 =>
          if data_in = '1' then
            state <= s2;
          else
            state <= s1;
          end if;
        when s2 =>
          if data_in = '1' then
            state <= s3;
          else
            state <= s2;
          end if;
        when s3 =>
          if data_in = '1' then
            state <= s0;
          else
            state <= s3;
          end if;
      end case;
    end if;
  end process;

  -- Output depends solely on the current state
  process (state)
  begin

    case state is
      when s0 =>
        data_out <= "00";
      when s1 =>
        data_out <= "01";
      when s2 =>
        data_out <= "10";
      when s3 =>
        data_out <= "11";
    end case;
  end process;

end rtl;


-- User-Encoded State Machine

library ieee;
use ieee.std_logic_1164.all;

entity user_encod is

  port
  (
    updown : in std_logic;
    clock  : in std_logic;
    lsb    : out std_logic;
    msb    : out std_logic
  );

end entity;

architecture rtl of user_encod is

  -- Build an enumerated type for the state machine
  type count_state is (zero, one, two, three);

  -- Registers to hold the current state and the next state
  signal present_state, next_state : count_state;

  -- Attribute to declare a specific encoding for the states
  attribute syn_encoding                : string;
  attribute syn_encoding of count_state : type is "11 01 10 00";

begin

  -- Determine what the next state will be, and set the output bits
  process (present_state, updown)
  begin
    case present_state is
      when zero =>
        if (updown = '0') then
          next_state <= one;
          lsb        <= '0';
          msb        <= '0';
        else
          next_state <= three;
          lsb        <= '1';
          msb        <= '1';
        end if;
      when one =>
        if (updown = '0') then
          next_state <= two;
          lsb        <= '1';
          msb        <= '0';
        else
          next_state <= zero;
          lsb        <= '0';
          msb        <= '0';
        end if;
      when two =>
        if (updown = '0') then
          next_state <= three;
          lsb        <= '0';
          msb        <= '1';
        else
          next_state <= one;
          lsb        <= '1';
          msb        <= '0';
        end if;
      when three =>
        if (updown = '0') then
          next_state <= zero;
          lsb        <= '1';
          msb        <= '1';
        else
          next_state <= two;
          lsb        <= '0';
          msb        <= '1';
        end if;
    end case;
  end process;

  -- Move to the next state
  process
  begin
    wait until rising_edge(clock);
    present_state <= next_state;
  end process;

end rtl;