VIVADO 11.Divider除法器IP1、测试环境2、IP接口3、参数配置4、测试代码

1、测试环境

vivado 2018.2

2、IP接口

时钟使能 与 复位可定制。

3、参数配置

• Algorithm Type

  LUTMult	This is recommended for operand widths less than or equal to 12 bits This implementation uses DSP slices, block RAM and a small amount of FPGA logic primitives (registers and LUTs).
  Radix-2	This is recommended for operand widths less than around 16 bits or for applications requiring high throughput。 The Radix2 solution does not use DSP or block RAM primitives, so this implementation is recommended when these primitives are needed elsewhere.
  High Radix	High Radix division with prescaling. This is recommended for operand widths greater than a

最后

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